The custom image processor project focused on creating a highly efficient processor at the datapath level. The processor is specifically optimized to run custom instructions that are tailored to image processing algorithms. By incorporating additional datapath components for algorithm-specific assembly instructions, the processor achieves an efficient cycle count for the image processing algorithms.

The project was developed by three electrical and computer engineering majors for a class competition. The processor was implemented using Verilog hardware description language. Verilog provided a powerful toolset to translate the architectural design into a register-transfer level representation, specifying the various datapath elements, control units, and interconnections. The custom instructions were carefully defined and implemented using Verilog modules. Additionally, the team utilized Verilog for simulation and verification, creating testbenches to validate the processor's performance and functionality. By utilizing Verilog as the programming language, the team demonstrated their proficiency in digital design and HDL programming, ultimately producing a high-quality custom image processor that won the class competition for minimum cycle count.

The custom image processor comprises four key features, each playing a critical role in its functionality and performance:

4-Core Processor: The image processor contains four individual cores, enabling parallel processing of image data to enhance overall performance.

6-Stage Pipeline: Each core in the processor incorporates a six-stage pipeline architecture, consisting of different stages like instruction fetch, instruction decode, execution, memory access, write-back, and control, allowing efficient instruction execution and reducing pipeline hazards.

MIPS Architecture: The processor is based on the 32-bit MIPS architecture. It also features a set of custom instructions meant to minimize cycle count for the class competition.

Xilinx Artix-7 FPGA: The custom image processor was designed to be implemented and validated on the Xilinx Artix-7 FPGA platform. The FPGA provides flexibility for hardware development and offers ample resources for accommodating the processor's complex design.

The link below can be used to view the code on Github.